1. Field of the Invention
The present invention relates generally to packaged semiconductor devices with a low profile. More specifically, the invention pertains to wafer-level packages having a true chip profile or both a chip profile and a chip footprint.
The dimensions of many different types of state-of-the-art electronic devices are ever decreasing. To reduce the dimensions of electronic devices, the structures by which the microprocessors, memory devices, other semiconductor devices, and other electronic components of these devices are packaged and assembled with carriers, such as circuit boards, must become more compact. In general, the goal is to economically produce a chip-scale package (CSP) of the smallest size possible, and with conductive structures, such as leads, pins, or conductive bumps, which do not significantly contribute to the overall size in the X, Y, or Z dimensions, all while maintaining a very high performance level.
One approach to reducing the sizes of assemblies of semiconductor devices and circuit boards has been to minimize the profiles of the semiconductor devices and other electronic components upon carrier substrates (e.g., circuit boards) so as to reduce the distances the semiconductor devices protrude from the carrier substrates. Various types of packaging technologies have been developed to facilitate orientation of semiconductor devices upon carrier substrates in this manner.
Conventionally, semiconductor device packages are multilayered structures, typically including a bottom layer of encapsulant material, a carrier (e.g., leads, a circuit board, etc.), a semiconductor, die, and a top layer of encapsulant material, for example. In addition, the leads, conductive bumps, or pins of conventional semiconductor device packages, which electrically connect such packages to carrier substrates, as well as provide support for the packages, are sometimes configured to space the semiconductor device packages apart from a carrier substrate. As a result, the overall thicknesses of these semiconductor device packages and the distances the packages protrude from carrier substrates are greater than is often desired for use in state-of-the-art electronic devices.
Wafer-level packaging (WLP) refers to packaging of an electronic component while it is still part of a wafer. The packages that are formed by WLP processes are generally considered to be “chip-sized” packages, at least with respect to the lateral X and Y dimensions, i.e., “footprint”, but typically have somewhat enlarged profiles in the Z dimension due to the solder balls, pins, or other conductive structures that protrude therefrom. Likewise, modules of stacked dice may use interdie connections comprising solder balls, pins, etc., which substantially contribute to the overall Z dimension, i.e., profile.
“Flip-chip” technology, as originating with controlled-collapse chip connection (C-4) technology, is an example of an assembly and packaging technology that results in a semiconductor device being oriented substantially parallel to a carrier substrate, such as a circuit board. In flip-chip technology, the bond pads or contact pads of a semiconductor device are arranged in an array over a major surface of the semiconductor device. Flip-chip techniques are applicable to both bare and packaged semiconductor devices. A packaged flip-chip type semiconductor device, which typically has solder balls arranged in a so-called “ball grid array” (BGA) connection pattern, typically includes a semiconductor die and a carrier substrate, which is typically termed an “interposer”. The interposer may be positioned adjacent either the back side of the semiconductor die or the active (front) surface thereof.
When the interposer is positioned adjacent the back side of the semiconductor die, the bond pads of the semiconductor die are typically electrically connected by way of wire bonds or other intermediate conductive elements to corresponding contact areas on a top side of the interposer. These contact areas communicate with corresponding bumped contact pads on the back side of the interposer. This type of flip-chip assembly is positioned adjacent a higher-level carrier substrate with the back side of the interposer facing the carrier substrate.
If the interposer is positioned adjacent the active surface of the semiconductor die, the bond pads of the semiconductor die may be electrically connected to corresponding contact areas on an opposite, top surface of the interposer by way of intermediate conductive elements that extend through one or more holes formed in the interposer. Again, the contact areas communicate with corresponding contact pads on the interposer. In this type of flip-chip semiconductor device assembly, however, the contact pads are also typically located on the top surface of the interposer. Accordingly, this type of flip-chip assembly is positioned adjacent a higher-level carrier substrate, such as a printed circuit board, by orienting the interposer with the top surface facing the carrier substrate.
In each of the foregoing types of flip-chip semiconductor devices, the contact pads of the interposer are disposed in an array that has a footprint that mirrors an arrangement of corresponding terminals or other contact regions formed on a carrier substrate. Each of the bond (on bare flip-chip semiconductor dice) or contact (on flip-chip packages) pads and its corresponding terminal may be electrically connected to one another by way of a conductive structure, such as a solder ball, that also spaces the interposer some distance away from the carrier substrate.
The space between the interposer and the carrier substrate may be left open or filled with a so-called “underfill” dielectric material that provides additional electrical insulation between the semiconductor device and the carrier substrate. In addition, each of the foregoing types of flip-chip semiconductor devices may include an encapsulant material covering portions or substantially all of the interposer and/or the semiconductor die.
The thicknesses of conventional flip-chip type packages having ball grid array connection patterns are defined by the combined thicknesses of the semiconductor die, the interposer, the adhesive material therebetween, and the conductive structures (e.g., solder balls) that protrude above the interposer or the semiconductor die. As with the flat packages, conventional flip-chip type packages are often undesirably thick for use in small, thin, state-of-the-art electronic devices. Furthermore, use of this general construction method for producing a stacked multichip module (MCM) results in a relatively high-profile, large footprint device.
Thinner, or low-profile, flip-chip type packages have been developed which include interposers or other carriers with recesses that are configured to receive at least a portion of the profiles of semiconductor devices. While interposers that include recesses for partially receiving semiconductor devices facilitate the fabrication of thinner flip-chip type packages, the semiconductor dice of these packages, as well as intermediate conductive elements that protrude beyond the outer surfaces of either the semiconductor dice or the interposers, undesirably add to the thicknesses of these packages.
U.S. Pat. Nos. 5,541,450 and 5,639,695, both issued to Jones et al. (hereinafter “the '450 and '695 patents”), disclose another type of flip-chip type package, which includes an interposer with a semiconductor die receptacle extending completely therethrough. The '695 patent teaches a package that may be formed by securing a semiconductor die directly to a carrier substrate and electrically connecting the interposer to the carrier substrate before the semiconductor die is electrically connected to the interposer. The semiconductor die, intermediate conductive elements that connect bond pads of the semiconductor die to corresponding contact areas on the interposer, and regions of the interposer adjacent the receptacle may then be encapsulated. While this method results in a very low-profile flip-chip type package, the package cannot be tested separately from the carrier substrate. As a result, if the package is unreliable, it may also be necessary to discard the carrier substrate and any other components thereon. Moreover, the packaging method of the '695 patent complicates the process of connecting semiconductor devices and other electronic components to a carrier substrate. In addition, it should be noted that in order to obtain a low-profile package, it may be necessary to sacrifice footprint compactness. The footprint area of such a low-profile package may be significantly greater than the area of the semiconductor die thereof.
Thus, there is a need for semiconductor device packages that have dimensions that closely resemble the corresponding dimensions of a semiconductor device of such packages, as well as for packaging methods.